Why HPSC Is a Big Deal for Space Exploration

Spacecraft processors have historically prioritized survivability over performance because the space environment—radiation, extreme temperatures, vibration, and multi-year missions—demands reliability that commercial processors cannot offer. That trade-off has limited computing capacity, but future missions require more onboard autonomy, sophisticated instruments, and faster decision-making, creating a clear need for a new approach.

NASA's HPSC project addresses this with a 64-bit multi-core system-on-chip built in partnership with Microchip Technology as the PIC64-HPSC. It combines cache-coherent multi-core processing, radiation-hardened-by-design engineering, fault-tolerant operational capabilities, and integrated high-speed networking. The architecture supports virtualization, AI/ML workloads, PCIe, Compute Express Link (CXL), Ethernet, time-sensitive networking, cryptography, and includes integrated 240-gig high-speed connectivity. Radiation-hardened and radiation-tolerant variants accommodate different mission classes, and unused functions can be powered down.

NASA expects HPSC to deliver more than a hundredfold improvement in performance per watt compared with current space-qualified systems; every milliwatt saved can be redirected to instruments, communications, or mobility systems. The processor entered a testing phase at JPL in May 2026, and its capabilities could enable entirely new ways to explore the solar system.